Aldec's Graphical Cross-Probing Speeds Design Debugging
Henderson Nevada, November 5th, 2001-- Aldec, Inc., a leading supplier of HDL design entry and verification software for application specific integrated circuits (ASICs) and field programmable gate arrays (FPGAs) announced today the release of the graphical cross-probing utility for its Active-HDL simulator, which allows concurrent troubleshooting of HDL and graphical design representations. Designers can modify either the graphical or textual design representation, accelerating design development.
Supported by code-to-graphics and graphics-to-code converters, the graphical cross-probe utility allows users to modify their designs in the preferred representation. When the designer highlights a portion of the design in the Block Diagram Editor, the appropriate source code area is displayed in the HDL editor for review and editing. Any HDL changes are instantly back-annotated and the designer can continue without having to switch back to the graphical image.
Since the Block Diagram Editor supports cross probing between the diagram and the generated code, it provides greater control over the design from the earliest stages and allows designers to link such diagram elements as wires, buses and components with the corresponding HDL code.
In addition to enabling designers to change between the graphical and textual representations of their code, Active-HDL also enables them to trace the HDL signals through the entire design regardless of the design representation. This allows users to quickly identify errors in the code, even in the most complex designs. The user can point to any signal in the text or graphic and the list of signal sources and drivers will be instantly displayed in the local menu.
Availability
Active-HDL's Cross Probing from the Block Diagram Editor to HDL code is available now. The product is available as either a floating or node-lock license and includes Active-HDL's Project Manager, HDL Editor, State Machine Editor, and Block Diagram & Schematic Editors, Automatic Testbench Generation, Waveform Viewer/Editor, and a choice of VHDL, Verilog or mixed VHDL/Verilog/EDIF simulation. All sales include one year of product maintenance. To receive your FREE evaluation copy, contact Aldec at www.aldec.com.
About Aldec
Aldec, Inc. has offered PC and Workstation-based design entry and simulation solutions to FPGA and ASIC designers for more than 16 years. During this time, Aldec has signed several OEM agreements with IC vendors, such as Xilinx, Inc. (NASDAQ:XLNX) and Cypress Semiconductor Corp. (NYSE:CY). Aldec, headquartered in Henderson, Nevada, produces a universal suite of Windows, Linux and UNIX-based EDA tools that allow design engineers to implement their designs using several different design entry methods (Schematic Capture, State Machine, Block Diagram, VHDL, Verilog or ABEL). Aldec incorporates patented simulation technology and several design entry tools to provide a complete design entry and simulation solution. Founded in 1984, the company continues to evolve in the EDA market as the fastest growing verification company in the world. Additional information about Aldec is available at http://www.aldec.com.
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